Generally, semiconductor devices include a plurality of circuits that form an integrated circuit (IC) fabricated on a semiconductor substrate. A complex network of signal paths will normally be routed to connect the circuit elements distributed on the surface of the substrate. Efficient routing of these signals across the device requires formation of multilevel or multilayered schemes, such as, for example, single or dual damascene wiring structures. The wiring structure typically includes copper, Cu, since Cu based interconnects provide higher speed signal transmission between large numbers of transistors on a complex semiconductor chip as compared with aluminum, Al, based interconnects.
Within a typical interconnect structure, metal vias run perpendicular to the semiconductor substrate and metal lines run parallel to the semiconductor substrate. Further enhancement of the signal speed and reduction of signals in adjacent metal lines (known as “crosstalk”) are achieved in today's IC product chips by embedding the metal lines and metal vias (e.g., conductive features) in a dielectric material having a dielectric constant of less than 4.0.
That is, in order to reduce the interconnect portion of circuit delay, conventional dielectric materials having a dielectric constant of about 4.0 or greater such as, for example, silicon dioxide, have been replaced with dense lower-k dielectric materials having a dielectric constant of less than 4.0, preferably less than 3.5. It is noted that all dielectric constants mentioned throughout this application are relative to vacuum. For further performance improvement, more dielectric capacitance reduction is required for advanced devices.
Capacitance improvements can be made by replacing the dense low-k dielectric materials with porous low-k dielectric materials. Despite the improvement in capacitance, porous low-k dielectric materials have relatively weak mechanical properties as compared to dense dielectrics. Additionally, it is a significant challenge for current interconnects processing to integrate porous low-k dielectric materials with other module processes.
For example, the conventional chemical mechanical polishing (CMP) process has difficulty in planarizing a low mechanical-module porous dielectric, and the conventional physical vapor deposition (PVD) diffusion barrier deposition technology cannot offer reasonable coverage on the surface of the porous low-k dielectric material. That is, the conventional PVD process provides a discontinuous PVD liner on the exposed surfaces of the porous low-k dielectric material. It is noted that the presence of a discontinuous PVD liner around the conductive feature embedded in a porous low k dielectric material is a sever circuit reliability concern.
Referring back to dense low-k dielectric materials, the applicants have observed that an undercut profile, such as shown, in FIG. 1A, exists because of the etching rate difference between the dense low-k dielectric material and the oxide-containing hard mask material. A similar result may exist with some porous low-dielectric materials as well. Specifically, FIG. 1A shows a partially formed prior art interconnect structure 10 which includes a lower interconnect level 12A and an upper interconnect level 12B which are separated by a dielectric capping layer 20. The lower interconnect level 12A includes a first dielectric material 14A having at least one conductive feature represented by conductive material 18A embedded therein. A diffusion barrier 16A separates the conductive material 18A from the first dielectric material 14A. Atop the dielectric capping layer 20, is the upper interconnect level 12B which, at this stage of the prior art process, includes a patterned dense low-k dielectric material 14B and a patterned oxide-containing hard mask 22 located on a surface of the low-k dielectric material 14B. The undercut region is labeled as 24 in FIG. 1A.
This undercut profile results in poor conductor fill property in the final interconnect structure and leaves voids between the diffusion barrier and the interconnect conductive material. This is clearly seen in FIG. 1B (actual cross sectional photograph of a prior art interconnect structure) and 1C (actual top down view). The term ILD denotes the second dielectric material 14B mentioned above, barrier represents a second diffusion barrier that is formed in the opening of the patterned ILD, Cu represents the conductive material used in filling the openings. Reliability related issues may be caused by having the voids present inside the interconnect structure.
In view of the above, there is a need for providing a new and improved interconnect structure which overcomes all of the drawbacks mentioned above. That is, there is a need for providing a new and improved interconnect structure that has improved performance as well as enhanced reliability without changing the existing materials or the process flow significantly.